PIC18F4450T-I/ML【PDF 196/241 页】IC PIC MCU FLASH 8KX16 44QFN

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XMEGA A [MANUAL]

8077I–AVR–11/2012

interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a one to this

location.

Bit 4 – TRNIF: Channel n Transaction Complete Interrupt Flag

When a transaction on the DMA channel has been completed, the TRNIF flag will be set and the optional interrupt is

generated. When repeat is not enabled, the transaction is complete and TRNIFR is set after the block transfer. When

unlimited repeat is enabled, TRNIF is also set after each block transfer.

Since the DMA channel transaction n complete interrupt shares the interrupt address with the DMA channel error

interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a one to this

location.

Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level

These bits enable the interrupt for DMA channel transfer errors and select the interrupt level, as described in “Interrupts

and Programmable Multilevel Interrupt Controller” on page 125. The enabled interrupt will trigger for the conditions when

ERRIF is set.

Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level

These bits enable the interrupt for DMA channel transaction completes and select the interrupt level, as described in

“Interrupts and Programmable Multilevel Interrupt Controller” on page 125. The enabled interrupt will trigger for the

conditions when TRNIF is set.

5.14.3 ADDRCTRL – Address Control register

Bit 7:6 – SRCRELOAD[1:0]: Channel Source Address Reload

These bits decide the DMA channel source address reload according to Table 5-5. A write to these bits is ignored while

the channel is busy.

Table 5-5.

DMA channel source address reload settings.

Bit 5:4 – SRCDIR[1:0]: Channel Source Address Mode

These bits decide the DMA channel source address mode according to Table 5-6. These bits cannot be changed if the

channel is busy.

Bit

+0x02

SRCRELOAD[1:0]

SRCDIR[1:0]

DESTRELOAD[1:0]

DESTDIR[1:0]

Read/Write

R/W

Initial Value

SRCRELOAD[1:0]

Group Configuration

Description

NONE

No reload performed.

BLOCK

DMA source address register is reloaded with initial value at end of each

block transfer.

BURST

DMA source address register is reloaded with initial value at end of each

burst transfer.

TRANSACTION

DMA source address register is reloaded with initial value at end of each

transaction.

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